Programmable devices are well known. Generally, programmable devices, such as field programmable gate arrays (“FPGAs”), contain numerous soft logic elements that are configurable into logic blocks that implement customized functions. FPGAs offer a low-cost and flexible solution for customers desiring to implement their own functional modules. However, FPGAs generally run slower than, and require more power and a larger area compared to, hard logic solutions such as application specific integrated devices (“ASICs”). ASICs, on the other hand, are not programmable and therefore provide less flexibility to customers desiring to customize hardware after fabrication.
As such, hybrid devices have emerged that include both hard logic and soft logic. The hard logic usually implements standard functional blocks, likely to be used in a variety of applications, while the soft logic enables customized functionality. However, these devices are limited in function and flexibility. Specifically, hard logic blocks often operate in serial fashion, and there may be no opportunity to bypass individual blocks in favor of soft logic. Additionally, hard logic blocks largely operate in isolation, such that the internal functionality of individual hard logic blocks cannot be augmented with soft logic features. Accordingly, these hybrid devices still require customers to forgo the speed and low-power advantages of hard logic whenever the flexibility afforded by soft logic is desired.